This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-293620, filed Sep. 26, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more specifically to a voltage-variable differential type delay circuit that includes a voltage-variable differential type delay cell and a bias circuit, which can be applied to a voltage controlled oscillator that can vary its oscillation frequency in accordance with the level of the control voltage or a voltage controlled oscillator that can vary its delay time in accordance with the level of the control voltage.
2. Description of the Related Art
In accordance with an increase in processing speed of LSIs, there is an increasing demand that a voltage controlled oscillator (VCO), which is widely used as a clock generator for a phase locked loop (PLL) that generates a clock signal within a LSI chip, have an excellent noise tolerance characteristic property and les jitter of frequency.
An example of the VCO with les jitter is a differential type VCO with an improved noise tolerance characteristic, which is achieved by using a voltage variable differential type delay cell in order to cancel same-phase noises.
FIG. 9A illustrates a part of a conventional differential type VCO reported in xe2x80x9cISSCC 1996 DIGEST OF TECHNICAL PAPERS, PP. 130-131xe2x80x9d.
The differential type VCO includes a plurality (N-number) of voltage variable differential type delay elements 10 that are connected in a ring-like manner. (Note that only one stage portion is shown.) In the voltage variable delay cells 10 of each stage, bias voltages VCP and VCN are supplied from a bias circuit 90 to which a control voltage Vcont is input.
In the voltage variable delay cells 10 of each stage, a VCR (Voltage Controlled Resistor) 11 serving as a load resistor of a MOS differential type amplifier circuit is provided, a bias voltage VCP is input to a control terminal of the VCR 11, and a bias voltage VCN is input to a gate of an NMOS transistor 12 used as a current source of the MOS differential type amplifier circuit.
FIG. 9B is a circuit diagram that shows an example of the VCR 11 in the voltage variable delay cell 10 shown in FIG. 9A.
In the VCR 11, the first PMOS transistor P1 and the second PMOS transistor P2 are connected in parallel to each other, and the gate and drain of the second PMOS transistor P2 are connected to make a short circuit. A bias voltage VCP is input to the gate of the first PMOS transistor P1.
In the voltage variable delay element 10, the resistance of the VCR 11 is controlled in accordance with the bias voltage VCP and the current of the constant current source transistor 12 is controlled in accordance with the bias voltage VCN.
The bias circuit 90 is designed to supply the bias voltages VCP and VCN to the voltage variable delay element 10, and it comprises a replica circuit 21 (Replica), a buffer circuit (Buffer) 23, a MOS-type operational amplifier circuit 24 (Op-Amp) and a self bias circuitry 25.
In the replica circuit 21, a VCR 212 having a structure equivalent to that of the VCR 11 of the voltage variable delay element 10 is connected to an NMOS transistor 211 via an NMOS transistor 213 that is normally ON, and the VCR 212 serves as a load resistor of the NMOS transistor 211. The resistance of the VCR 212 is controlled in accordance with the control voltage Vcont.
In the buffer circuit 23, a VCR 232 having a structure equivalent to that of the VCR 11 of the voltage variable delay element 10 is connected to an NMOS transistor 231 via an NMOS transistor 233 that is normally ON, and the VCR 232 serves as a load resistance of the NMOS transistor 231. A bias voltage VCP generated at one end on the NMOS transistor 231 side of the VCR 232 is supplied to the VCR 11 of the voltage variable delay element 10.
The operational amplifier 24 compares a voltage at one end on the NMOS transistor 211 side of the VCR 212 in the replica circuit 21, with the control voltage Vcont, and generates a bias voltage VCN, so as to control currents of the NMOS transistors 211 and 231 and the constant current source transistor 12 of the voltage variable delay element 10. The self bias circuitry 25 controls a current of the current source transistor 241 of the operational amplifier 24 on the basis of the bias voltage VCN. In this manner, a feedback control is conducted so as to equalize the voltage at the end on the NMOS transistor side of the VCR 212 in the replica circuit 21 and the control voltage Vcont with each other.
With the bias circuit 90 described above, the amplitude of the clock signal that propagates in the voltage variable delay element 10 (that is, the xe2x80x9cLxe2x80x9d level of the output node signal of the voltage variable delay element 10) is biased so that it is set to be a constant voltage Vcont even if the power voltage varies. Consequently, the variation in the amplitude of the clock signal to a voltage noise can be suppressed, and therefore the jitter of the oscillation frequency of the VCO is reduced.
The oscillation frequency f of the VCO shown in FIG. 9A can be expressed by the following formula:
1/f=Reff*Ceff=k*Ceff/(Vcontxe2x88x92Vt)xe2x80x83xe2x80x83(1)
where Reff represents an effective resistance, Ceff represents an effective capacitance of the voltage variable delay element 10, and Vt represents a threshold voltage of the PMOS transistors P1 and P2 that form the VCR 11. With the relationship formulated above, it is understood from FIG. 10 that the oscillation frequency f has such a characteristic that it linearly increases in proportional to a change in the control voltage Vcont.
With regard to the more recent LSIs, there has been a demand of higher frequency and lower voltage. Thus, the gain of the VCO (xcex94f/xcex94Vcont) that corresponds to the slope of the line illustrated in FIG. 10 is increased even higher. As the gain is increased, the frequency variation in reply to the variation of the control voltage increases, thereby deteriorating the noise tolerance characteristic.
According to a first aspect of the present invention, there is provided a semiconductor integrated circuit comprising a differential type voltage controlled delay cell including a first voltage controlled resistor element and a current source transistor of a MOS type differential amplifier circuit, the first voltage controlled resistor element functioning as a load resistor, wherein a resistance value of the first voltage controlled resistor element is controlled according to a first bias voltage, and a current of the current source transistor is controlled according to a second bias voltage; and a bias circuit including a first replica circuit and a second replica circuit, the first replica circuit having a structure equivalent to that of the voltage controlled delay cell, the second replica circuit having a structure equivalent to a structure in which the first voltage controlled resistor element of the voltage controlled delay cell is replaced by a constant resistor element, the bias circuit configured to generate and supply the first bias voltage and the second bias voltage to the voltage controlled delay cell.
According to a second aspect of the present invention, there is provided a semiconductor integrated circuit comprising a differential type voltage controlled delay cell including a first voltage controlled resistor element of a MOS type differential amplifier circuit and a constant resistor element which are connected in parallel to each other and a current source transistor of the MOS type differential amplifier circuit, the first voltage controlled resistor element and the constant resistor element functioning as load resistors, wherein a resistance value of the first voltage controlled resistor element is controlled according to a first bias voltage, and a current of the current source transistor is controlled according to a second bias voltage; and a bias circuit including a replica circuit having a structure equivalent to that of the voltage controlled delay cell, the bias circuit configured to generate and supply the first bias voltage and the second bias voltage to the voltage controlled delay cell.